View NPIC6C4894PW_8252828.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

1. general description the npic6c4894 is a 12-stage serial shift regist er. it has a storage latch associated with each stage for strobing data from the serial input (d) to the parallel open-drain outputs (qp0 to qp11). data is shifted on positive-goi ng clock (cp) transitions. the data in each shift register stage is transferred to the storage register when the latch enable (le) input is high. data in the storage register drives the gate of the output extended-drain nmos transistor whenever the output enable inpu t (oe) is high. a low on oe causes the outputs to assume a high-impedance off-state. operation of the oe input does not affect the state of the registers. two serial outputs (qs1 and qs2) are available for cascading a number of nic6c4894 devices. serial data is available at qs1 on positive-going clock edges to allow high-speed operation in cascaded systems with a fast clock rise time. the same serial data is available at qs2 on the next negative going clock edge. it is used for cascading npic6c4894 devices when the cl ock has a slow rise time. the open-drain outputs are 33 v/100 ma cont inuous current extended-drain nmos transistors designed for use in systems that require moderate load power such as leds. integrated voltage clamps in the outputs, provide protection ag ainst inductive transients. this protection makes the device suitable for power driver applications such as relays, solenoids and other low-current or medium-voltage loads. 2. features and benefits ? specified from ? 40 ? cto+125 ? c ? low r dson ? 12 power ednmos transistor output s of 100 ma continuous current ? 250 ma current limit capability ? output clamping voltage 33 v ? 30 mj avalanche energy capability ? low power consumption ? latch-up performance exceeds 100 ma per jesd 78 class ii level a ? esd protection: ? hbm js-2011 class 2 exceeds 2500 v ? cdm jesd22-c101e exceeds 1000 v npic6c4894 power logic 12-bit shift register; open-drain outputs rev. 1 ? 17 april 2014 product data sheet
npic6c4894 all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2014. all rights reserved. product data sheet rev. 1 ? 17 april 2014 2 of 21 nxp semiconductors npic6c4894 power logic 12-bit shift register; open-drain outputs 3. applications ? led sign ? graphic status panel ? fault status indicator 4. ordering information 5. functional diagram table 1. ordering information type number package temperature range name description version npic6c4894d ? 40 ? c to +125 ? c so20 plastic small outline package; 20 leads; body width 7.5 mm sot163-1 NPIC6C4894PW ? 40 ? c to +125 ? c tssop20 plastic thin shrink small outline package; 20 leads; body width 4.4 mm sot360-1 fig 1. logic symbol ddd 2( ' &3 /( 43 43 43 43 43 43 43 43 46 46 43 43 43 43
npic6c4894 all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2014. all rights reserved. product data sheet rev. 1 ? 17 april 2014 3 of 21 nxp semiconductors npic6c4894 power logic 12-bit shift register; open-drain outputs fig 2. functional diagram ddd 43 43 43 43 43 43 43 43 43 43 43 43 46 46 67$*(6+,)75(*,67(5 %,76725$*(5(*,67(5 23(1'5$,12873876 ' &3 /( 2( fig 3. schematic of all inputs fig 4. schematic of open-drain outputs (qpn) aaa-002550 gnd v cc ddd *1' 9 43q fig 5. logic diagram ddd 43 43 43 43 46 46 ' 46 ' &3 /( 2( 67$*(72 /$7&+ /( )) )) '4 4 '4 /$7&+ /( '4 /$7&+ 67$*( 67$*( /( '4 &3 ' &3
npic6c4894 all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2014. all rights reserved. product data sheet rev. 1 ? 17 april 2014 4 of 21 nxp semiconductors npic6c4894 power logic 12-bit shift register; open-drain outputs 6. pinning information 6.1 pinning 6.2 pin description fig 6. pin configuration so20 and tssop20 13,&& / ( 2 ( ' & 34 3 43 4 3 43 4 3 43 4 3 43 4 3 43 4 3 43 4 6 *1' 4 6 ddd 9 && table 2. pin description symbol pin description le 1 latch enable input d 2 serial data input cp 3 clock input qp0 to qp11 4, 5, 6, 7, 8, 9, 18, 17, 16, 15, 14, 13 parallel output gnd 10 ground (0 v) qs1 11 serial output qs2 12 serial output oe 19 output enable input v cc 20 supply voltage
npic6c4894 all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2014. all rights reserved. product data sheet rev. 1 ? 17 april 2014 5 of 21 nxp semiconductors npic6c4894 power logic 12-bit shift register; open-drain outputs 7. functional description [1] h = high voltage level; l = low voltage level; x = don?t care; ? = low-to-high clock transition; ? = high-to-low clock transition; z = high-impedance off-state. [2] q10s = the data in register stage 10 before the low to high clock transition. [3] q11s = the data in register stage 11 before the high to low clock transition. table 3. function table [1] at the positive clock edge, the information in the 10 th register stage is transferred to the 11 th register stage and the qs output control input parallel output serial output cp oe le d qp0 qpn qs1 [2] qs2 [3] ? l x x z z q10s no change ? l x x z z no change q11s ? h l x no change no change q10s no change ? hhl z qpn ? 1 q10s no change ? hhhl qpn ? 1 q10s no change ? h h h no change no change no change q11s fig 7. timing diagram ddd &3lqsxw 'lqsxw /(lqsxw 2(lqsxw lqwhuqdo46 )) 43rxwsxw lqwhuqdo46 )) 43rxwsxw vhuldo46 rxwsxw vhuldo46 rxwsxw
npic6c4894 all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2014. all rights reserved. product data sheet rev. 1 ? 17 april 2014 6 of 21 nxp semiconductors npic6c4894 power logic 12-bit shift register; open-drain outputs 8. limiting values [1] each power ednmos source is internally connected to gnd. [2] pulse duration ? 100 ? s and duty cycle ? 2 %. [3] v ds = 15 v; starting junction temperature (t j ) = 25 ? c; l = 1.5 h; avalanche current (i al ) = 200 ma. [4] for so20 package: above 25 ? c the value of p tot derates linearly with 12 mw/ ? c. for tssop20 package: above 25 ? c the value of p tot derates linearly with 10 mw/ ? c. table 4. limiting values in accordance with the absolute maximum rating system (iec 60134). voltages are referenced to gnd (ground = 0 v). symbol parameter conditions min max unit v cc supply voltage ? 0.5 +7.0 v v i input voltage ? 0.3 +7.0 v v ds drain-source voltage qpn [1] -+33 v v o output voltage qsn ? 0.5 +7.0 v i ik input clamping current v i < 0.5 v or v i > v cc + 0.5 v - ? 50 ma i ok output clamping current qsn; v o < 0.5 v or v o > v cc + 0.5 v - ? 100 ma i d(sd) source-drain diode current continuous - 250 ma pulsed [2] - 500 ma i d drain current t amb = 25 ?c continuous; each output; all outputs on - 100 ma pulsed; each output; all outputs on [2] - 250 ma i dm peak drain current single output; t amb = 25 ?c [2] - 250 ma e as non-repetitive avalanche energy single pulse; see figure 8 and figure 16 [3] -30 mj i al avalanche current see figure 8 and figure 16 [3] - 200 ma t stg storage temperature ? 65 +150 ?c p tot total power dissipation t amb = 25 ?c [4] so20 - 1500 mw tssop20 - 1250 mw t amb = 125 ?c [4] so20 - 300 mw tssop20 - 250 mw
npic6c4894 all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2014. all rights reserved. product data sheet rev. 1 ? 17 april 2014 7 of 21 nxp semiconductors npic6c4894 power logic 12-bit shift register; open-drain outputs 8.1 test circuit and waveform 9. recommended operating conditions [1] pulse duration ? 100 ? s and duty cycle ? 2 %. [2] technique should limit t j ? t amb to 10 ? c maximum. (1) the word generator has the following characteristics: t r ,t f ? 10 ns; z o = 50 ? . (2) the input pulse duration (t w ) is increased until peak current i al = 200 ma. energy test level is defined as: e as =i al ? v (br)dss ? t al /2 = 30 mj. fig 8. test circuit and waveform for measuring single-pulse avalanche energy ddd :25' *(1(5$ 725 '87 9 9 9 plq 9 o $/ p $ 9 %5'66 9 , 2 9 2 + *1' 2( /( ' &3 9 && 9 2 o 2 43q w z w $/ table 5. recommended operating conditions symbol parameter conditions min typ max unit v cc supply voltage 4.5 5.0 5.5 v v i input voltage 0 - 5.5 v i d drain current pulsed drain output current; v cc =5v; t amb = 25 ?c; all outputs on [1] [2] - - 250 ma t amb ambient temperature ? 40 - +125 ?c
npic6c4894 all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2014. all rights reserved. product data sheet rev. 1 ? 17 april 2014 8 of 21 nxp semiconductors npic6c4894 power logic 12-bit shift register; open-drain outputs 10. static characteristics [1] technique should limit t j ? t amb to 10 ? c maximum. [2] these parameters are measured with voltage-sensing contacts separate from the current-carrying contacts. [3] the output current is defined for a consistent comparison between devices from different sources. it is the current that pro duces a voltage drop of 0.5 v. table 6. static characteristics at recommended operating conditions un less otherwise specified; voltages ar e referenced to gnd (ground = 0 v). symbol parameter conditions t amb = 25 ?c t amb = ? 40 ? c to 125 ?c unit min typ max min typ max v ih high-level input voltage 0.85v cc -- ---v v il low-level input voltage - - 0.15v cc ---v v oh high-level output voltage qsn; v i =v ih or v il i o = ? 20 ? a; v cc = 4.5 v 4.4 4.49 - - - - v i o = ? 4ma; v cc = 4.5 v 4.0 4.2 - - - - v v ol low-level output voltage qsn; v i =v ih or v il i o =20 ? a; v cc = 4.5 v - 0.005 0.1 - - - v i o =4ma; v cc = 4.5 v - 0.3 0.5 - - - v i i input leakage current v cc = 5.5 v; v i =v cc or gnd - - ? 1- - - ? a v (br)dss drain-source breakdown voltage qpn; i o = 1 ma 33 37 - - - - v v sd source-drain voltage qpn; i o = 100 ma ? 1.2 ? 0.85 - - - - v i cc supply current v cc = 5.5 v; v i =v cc or gnd oe = low - 0.006 200 - - - ? a oe = high - 0.01 500 - - - ? a oe = low; cp = 5 mhz; see figure 15 and figure 17 -15 - - -ma i o output current qpn; v o = 0.5 v [1] [2] [3] - 140 - - - - ma i oz off-state output current qpn; v cc = 5.5 v; v ds = 30 v - 0.002 0.2 - 0.15 0.3 ? a r dson drain-source on-state resistance see figure 18 and figure 19 [1] [2] v cc = 4.5 v; i o = 50 ma - 2.7 9 - 4.3 12 ? v cc = 4.5 v; i o = 100 ma - 2.8 10 - - - ?
npic6c4894 all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2014. all rights reserved. product data sheet rev. 1 ? 17 april 2014 9 of 21 nxp semiconductors npic6c4894 power logic 12-bit shift register; open-drain outputs 11. dynamic characteristics [1] t pd is the same as t plh and t phl . [2] this is the maximum serial clock frequency assuming cascaded operation where seri al data is passed from one stage to a secon d stage. the clock period allows for cp qsn propagation delay and setup time plus some timing margin. [3] technique should limit t j ? t amb to 10 ? c maximum. [4] these parameters are measured with voltage-sensing contacts separate from the current-carrying contacts. table 7. dynamic characteristics at recommended operating conditions unless otherwise specified; voltages are refere nced to gnd (ground = 0 v); for test circuit, see figure 15 . symbol parameter conditions t amb = 25 ?c unit min typ max t pd propagation delay cp to qsn; see figure 9 [1] -5-ns t tlh low to high output transition time qpn; see figure 12 -60-ns qsn; see figure 9 -6-ns t thl high to low output transition time qpn; see figure 12 -18-ns qsn; see figure 9 -6-ns t plz low to off-state propagation delay cp, le and oe to qpn; i o = 75 ma; see figure 10 , figure 11 , figure 12 and figure 20 - 105 - ns t pzl off-state to low propagation delay cp, le and oe to qpn; i o = 75 ma; see figure 10 , figure 11 , figure 12 and figure 20 -10-ns f clk(max) maximum clock frequency cp; see figure 9 [2] 10 - - mhz t su set-up time d to cp; see figure 13 20 - - ns t h hold time d to cp; see figure 13 20 - - ns t w pulse width cp, le; see figure 9 and figure 11 40 - - ns t rr reverse recovery time i o = ? 100 ma; di/dt = 10 a/ ? s; see figure 14 [3] [4] - 120 - ns t a reverse recovery current rise time i o = ? 100 ma; di/dt = 10 a/ ? s; see figure 14 [3] [4] - 100 - ns
npic6c4894 all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2014. all rights reserved. product data sheet rev. 1 ? 17 april 2014 10 of 21 nxp semiconductors npic6c4894 power logic 12-bit shift register; open-drain outputs 11.1 waveforms and test circuits measurement points are given in table 8 . v ol and v oh are typical output voltage levels that occur with the output load. fig 9. propagation delay clock (cp) to output (qs1, qs2), clock pulse width, maximum clock frequency and output transition time ddd w 3+/ i fonpd[ 9 0 9 0 9 , *1' w : w : w 3/+ w 3+/ &3lqsxw 46rxwsxw 46rxwsxw w 7/+ w 7+/ 9 0 w 7+/ w 7/+ 9 2+ 9 2+ 9 2/ 9 2/ measurement points are given in table 8 . v ol and v oh are typical output voltage levels that occur with the output load. fig 10. propagation delay cl ock (cp) to output (qpn) ddd 9 0 9 ; 9 , *1' 9 2/ w 3/= w 3=/ 9 < &3lqsxw 43qrxwsxw 9
npic6c4894 all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2014. all rights reserved. product data sheet rev. 1 ? 17 april 2014 11 of 21 nxp semiconductors npic6c4894 power logic 12-bit shift register; open-drain outputs measurement points are given in table 8 . v ol is the typical output voltage level that occurs with the output load. fig 11. latch enable (le) to output (qpn) propagation delays and the latch enable pulse width ddd &3lqsxw w : w 3/= w 3=/ 9 0 9 0 9 ; 9 < 9 , *1' 9 , /(lqsxw 9 2/ 43qrxwsxw *1' 9 measurement points are given in table 8 . v ol is the typical output voltage level that occurs with the output load. fig 12. output enable (oe) to output (qpn) and output transition time ddd 2(lqsxw 43qrxwsxw 9 , 9 0 9 ; 9 ; w 3/= w 3=/ rxwsxwv hqdeohg rxwsxwv hqdeohg rxwsxwv glvdeohg *1' 9 9 2/ 9 < 9 < w 7/+ w 7+/
npic6c4894 all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2014. all rights reserved. product data sheet rev. 1 ? 17 april 2014 12 of 21 nxp semiconductors npic6c4894 power logic 12-bit shift register; open-drain outputs measurement points are given in table 8 . the shaded areas indicate when the input is per mitted to change for predictable output performance. v ol is the typical output voltage level that occurs with the output load. fig 13. set-up and hold times ddd 9 , 9 , 9 0 w vx w k w k w vx 9 0 *1' *1' 9 &3lqsxw 'lqsxw 43qrxwsxw 9 2/ table 8. measurement points supply voltage input output v cc v m v m v x v y 5 v 0.5v cc 0.5v ds 0.1v ds 0.9v ds (1) the open-drain qpn terminal under test is connected to testpoin t k. all other terminals are connected together and connected to testpoint a. (2) the v i amplitude and r g are adjusted for di/dt = 10 a/ ? s. a v i double-pulse train is used to set i o = 0.1 a, where t 1 = 10 ? s, t 2 = 7 ? s and t 3 = 3 ? s. fig 14. test circuit and waveform for measuring reverse recovery current ddd , 2 '87 43q 9 gulyhu 5 * * ?) 9 p+ . $ w w w 9 , $ glgw $?v , 2 w d w uu ri, 5 0 , 50
npic6c4894 all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2014. all rights reserved. product data sheet rev. 1 ? 17 april 2014 13 of 21 nxp semiconductors npic6c4894 power logic 12-bit shift register; open-drain outputs [1] do not connect r l2 when measuring the supply current (i cc ). (1) the word generator has the following characteristics: t r , t f ? 10 ns; t w = 300 ns; pulsed repetition rate (prr) = 5 khz; z o = 50 ? . (2) c l includes probe and jig capacitance. test data is given in table 9 . definitions for test circuit: v ext = external voltage for measuring switching times. r l = load resistance. c l = load capacitance including jig and probe capacitance. fig 15. test circuit for measuring switching times ddd w : w : 9 0 qhjdwlyh sxovh srvlwlyh sxovh 9 , 9 9 9 , 9 0 9 0 9 0 w i w u w u w i *1' :25' *(1 (5$725 9 && 9 43q 9 (;7 9 5 / & / ' 2( &3 /( 5 / & / 46q table 9. test data supply voltage input load v i t r , t f v m c l r l1 r l2 [1] 5v 5v ? 10 ns 50% 30 pf 200 ? 2 k ?
npic6c4894 all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2014. all rights reserved. product data sheet rev. 1 ? 17 april 2014 14 of 21 nxp semiconductors npic6c4894 power logic 12-bit shift register; open-drain outputs t amb = 25 ? c; v cc = 5 v. t amb = ?40 ? c to 125 ? c; v cc = 5 v. fig 16. avalanche current (peak) versus time duration of avalanche fig 17. supply current versus frequency t al (ms) 10 -1 10 1 aaa-002562 10 -1 1 i al (a) 10 -2 i o 0+] ddd , && p$ v cc = 4.5 v; v i = v cc or gnd. (1) t amb = 125 ?c (2) t amb = 85 ? c (3) t amb = 25 ? c (4) t amb = ?40 ? c v i = v cc or gnd; i o = 50 ma. (1) t amb = 125 ?c (2) t amb = 85 ? c (3) t amb = 25 ? c (4) t amb = ?40 ? c fig 18. drain-source on-state resistance versus drain current fig 19. static drain-source on-state resistance versus supply voltage , 2 p$ ddd 5 '6rq 9 && 9 ddd 5 '6rq
npic6c4894 all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2014. all rights reserved. product data sheet rev. 1 ? 17 april 2014 15 of 21 nxp semiconductors npic6c4894 power logic 12-bit shift register; open-drain outputs v cc = 5 v; i o = 75 ma, this technique should limit t j ? t amb to 10 ? c maximum. (1) t plz . (2) t tlh . (3) t thl . (4) t pzl . fig 20. switching time versus temperature 7 dpe ?& ddd w qv
npic6c4894 all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2014. all rights reserved. product data sheet rev. 1 ? 17 april 2014 16 of 21 nxp semiconductors npic6c4894 power logic 12-bit shift register; open-drain outputs 12. package outline fig 21. package outline sot163-1 (so20) 81,7 $ pd[ $ $ $ e s f ' ( h + ( / / s 4 = \ z y 5()(5(1&(6 287/,1( 9(56,21 (8523($1 352-(&7,21 ,668('$7( ,(& -('(& -(,7$ pp lqfkhv r r ',0(16,216lqfkglphqvlrqvduhghulyhgiurpwkhruljlqdoppgl phqvlrqv 1rwh 3odvwlfruphwdosurwuxvlrqvripplqfkpd[lpxp shuvlghduhqrwlqfoxghg 627 z 0 e s ghwdlo; = h ' \ ( 06 slqlqgh[ pp vfdoh ; $ $ $ + ( / s 4 ( f / y 0 $ $ $ 62sodvwlfvpdoorxwolqhsdfndjhohdgverg\zlgwkp p 627
npic6c4894 all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2014. all rights reserved. product data sheet rev. 1 ? 17 april 2014 17 of 21 nxp semiconductors npic6c4894 power logic 12-bit shift register; open-drain outputs fig 22. package outline sot360-1 (tssop20) 81,7 $ $ $ e s f ' ( h + ( / / s 4 = \ z y 5()(5(1&(6 287/,1( 9(56,21 (8523($1 352-(&7,21 ,668('$7( ,(& -('(& -(,7$ pp r r ',0(16,216ppduhwkhruljlqdoglphqvlrqv 1rwhv 3odvwlfruphwdosurwuxvlrqvripppd[lpxpshuvlghduh qrwlqfoxghg 3odvwlflqwhuohdgsurwuxvlrqvripppd[lpxpshuvlghdu hqrwlqfoxghg 627 02 z 0 e s ' = h slqlqgh[ $ $ $ / s 4 ghwdlo; / $ + ( ( f y 0 $ ; $ \ pp vfdoh 76623sodvwlfwklqvkulqnvpdoorxwolqhsdfndjhohdgve rg\zlgwkpp 627 $ pd[
npic6c4894 all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2014. all rights reserved. product data sheet rev. 1 ? 17 april 2014 18 of 21 nxp semiconductors npic6c4894 power logic 12-bit shift register; open-drain outputs 13. abbreviations 14. revision history table 10. abbreviations acronym description cdm charged device model cmos complementary metal oxide semiconductor dut device under test ednmos extended drain negative metal oxide semiconductor esd electrostatic discharge hbm human body model ttl transistor-transistor logic table 11. revision history document id release date data sheet status change notice supersedes npic6c4894 v.1 20140417 product data sheet - -
npic6c4894 all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2014. all rights reserved. product data sheet rev. 1 ? 17 april 2014 19 of 21 nxp semiconductors npic6c4894 power logic 12-bit shift register; open-drain outputs 15. legal information 15.1 data sheet status [1] please consult the most recently issued document before initiating or completing a design. [2] the term ?short data sheet? is explained in section ?definitions?. [3] the product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple device s. the latest product status information is available on the internet at url http://www.nxp.com . 15.2 definitions draft ? the document is a draft versi on only. the content is still under internal review and subject to formal approval, which may result in modifications or additions. nxp semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall hav e no liability for the consequences of use of such information. short data sheet ? a short data sheet is an extract from a full data sheet with the same product type number(s) and title. a short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. for detailed and full information see the relevant full data sheet, which is available on request vi a the local nxp semiconductors sales office. in case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail. product specification ? the information and data provided in a product data sheet shall define the specification of the product as agreed between nxp semiconductors and its customer , unless nxp semiconductors and customer have explicitly agreed otherwis e in writing. in no event however, shall an agreement be valid in which the nxp semiconductors product is deemed to offer functions and qualities beyond those described in the product data sheet. 15.3 disclaimers limited warranty and liability ? information in this document is believed to be accurate and reliable. however, nxp semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such info rmation. nxp semiconductors takes no responsibility for the content in this document if provided by an information source outside of nxp semiconductors. in no event shall nxp semiconductors be liable for any indirect, incidental, punitive, special or consequential damages (including - without limitation - lost profits, lost savings, business interruption, costs related to the removal or replacement of any products or rework charges) whether or not such damages are based on tort (including negligence), warranty, breach of contract or any other legal theory. notwithstanding any damages that customer might incur for any reason whatsoever, nxp semiconductors? aggregate and cumulative liability towards customer for the products described herein shall be limited in accordance with the terms and conditions of commercial sale of nxp semiconductors. right to make changes ? nxp semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. this document supersedes and replaces all information supplied prior to the publication hereof. suitability for use ? nxp semiconductors products are not designed, authorized or warranted to be suitable for use in life support, life-critical or safety-critical systems or equipment, nor in applications where failure or malfunction of an nxp semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. nxp semiconductors and its suppliers accept no liability for inclusion and/or use of nxp semiconducto rs products in such equipment or applications and therefore such inclusion and/or use is at the customer?s own risk. applications ? applications that are described herein for any of these products are for illustrative purpos es only. nxp semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. customers are responsible for the design and operation of their applications and products using nxp semiconductors products, and nxp semiconductors accepts no liability for any assistance with applications or customer product design. it is customer?s sole responsibility to determine whether the nxp semiconductors product is suitable and fit for the customer?s applications and products planned, as well as fo r the planned application and use of customer?s third party customer(s). customers should provide appropriate design and operating safeguards to minimize the risks associated with their applications and products. nxp semiconductors does not accept any liability related to any default, damage, costs or problem which is based on any weakness or default in the customer?s applications or products, or the application or use by customer?s third party customer(s). customer is responsible for doing all necessary testing for the customer?s applic ations and products using nxp semiconductors products in order to av oid a default of the applications and the products or of the application or use by customer?s third party customer(s). nxp does not accept any liability in this respect. limiting values ? stress above one or more limiting values (as defined in the absolute maximum ratings system of iec 60134) will cause permanent damage to the device. limiting values are stress ratings only and (proper) operation of the device at these or any other conditions above those given in the recommended operating conditions section (if present) or the characteristics sections of this document is not warranted. constant or repeated exposure to limiting values will permanently and irreversibly affect the quality and reliability of the device. terms and conditions of commercial sale ? nxp semiconductors products are sold subject to the gener al terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms , unless otherwise agreed in a valid written individual agreement. in case an individual agreement is concluded only the terms and conditions of the respective agreement shall apply. nxp semiconductors hereby expressly objects to applying the customer?s general terms and conditions with regard to the purchase of nxp semiconducto rs products by customer. no offer to sell or license ? nothing in this document may be interpreted or construed as an offer to sell products t hat is open for acceptance or the grant, conveyance or implication of any lic ense under any copyrights, patents or other industrial or intellectual property rights. document status [1] [2] product status [3] definition objective [short] data sheet development this document contains data from the objecti ve specification for product development. preliminary [short] data sheet qualification this document contains data from the preliminary specification. product [short] data sheet production this document contains the product specification.
npic6c4894 all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2014. all rights reserved. product data sheet rev. 1 ? 17 april 2014 20 of 21 nxp semiconductors npic6c4894 power logic 12-bit shift register; open-drain outputs export control ? this document as well as the item(s) described herein may be subject to export control regu lations. export might require a prior authorization from competent authorities. non-automotive qualified products ? unless this data sheet expressly states that this specific nxp semicon ductors product is automotive qualified, the product is not suitable for automotive use. it is neither qualified nor tested in accordance with automotive testing or application requirements. nxp semiconductors accepts no liabili ty for inclusion and/or use of non-automotive qualified products in automotive equipment or applications. in the event that customer uses t he product for design-in and use in automotive applications to automotive specifications and standards, customer (a) shall use the product without nxp semiconductors? warranty of the product for such automotive applicat ions, use and specifications, and (b) whenever customer uses the product for automotive applications beyond nxp semiconductors? specifications such use shall be solely at customer?s own risk, and (c) customer fully indemnifies nxp semiconductors for any liability, damages or failed product claims resulting from customer design and use of the product for automotive app lications beyond nxp semiconductors? standard warranty and nxp semiconduct ors? product specifications. translations ? a non-english (translated) version of a document is for reference only. the english version shall prevail in case of any discrepancy between the translated and english versions. 15.4 trademarks notice: all referenced brands, produc t names, service names and trademarks are the property of their respective owners. 16. contact information for more information, please visit: http://www.nxp.com for sales office addresses, please send an email to: salesaddresses@nxp.com
nxp semiconductors npic6c4894 power logic 12-bit shift register; open-drain outputs ? nxp semiconductors n.v. 2014. all rights reserved. for more information, please visit: http://www.nxp.com for sales office addresses, please se nd an email to: salesaddresses@nxp.com date of release: 17 april 2014 document identifier: npic6c4894 please be aware that important notices concerning this document and the product(s) described herein, have been included in section ?legal information?. 17. contents 1 general description . . . . . . . . . . . . . . . . . . . . . . 1 2 features and benefits . . . . . . . . . . . . . . . . . . . . 1 3 applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 4 ordering information . . . . . . . . . . . . . . . . . . . . . 2 5 functional diagram . . . . . . . . . . . . . . . . . . . . . . 2 6 pinning information . . . . . . . . . . . . . . . . . . . . . . 4 6.1 pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 6.2 pin description . . . . . . . . . . . . . . . . . . . . . . . . . 4 7 functional description . . . . . . . . . . . . . . . . . . . 5 8 limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 6 8.1 test circuit and waveform . . . . . . . . . . . . . . . . . 7 9 recommended operating conditions. . . . . . . . 7 10 static characteristics. . . . . . . . . . . . . . . . . . . . . 8 11 dynamic characteristics . . . . . . . . . . . . . . . . . . 9 11.1 waveforms and test circuits . . . . . . . . . . . . . . 10 12 package outline . . . . . . . . . . . . . . . . . . . . . . . . 16 13 abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . 18 14 revision history . . . . . . . . . . . . . . . . . . . . . . . . 18 15 legal information. . . . . . . . . . . . . . . . . . . . . . . 19 15.1 data sheet status . . . . . . . . . . . . . . . . . . . . . . 19 15.2 definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 15.3 disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 15.4 trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 20 16 contact information. . . . . . . . . . . . . . . . . . . . . 20 17 contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

▲Up To Search▲

Price & Availability of NPIC6C4894PW

	To Download NPIC6C4894PW Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .